De Somno Et Insomniis. La Vida Monástica a Través del Lecho y los Procesos del S González Dávila, María Angélica; Ríos Espinosa, María Cristi Bonilla Artigas Editores |
Sobre la Animalidad (Y Otros Textos Afines de Política Contemporánea) Villegas Contreras, Armando Bonilla Artigas Editores |
Antropologías Feministas en México: Epistemologías, Éticas, Prácticas y Miradas Berrio, Castañeda, Goldsmith, Ruiz, Salas y Valladares Bonilla Artigas Editores |
Experiencias de Bioconstrucción: Conceptos Generales y Visiones Desde México Caballero Cervantes, Alejandra; Luis Fernando Guerrero Baca Bonilla Artigas Editores |
¿Cómo Comprender Lo Social Para Colaborar en Su Cambio? Diego Quintana, Roberto Bonilla Artigas Editores |
Libertades Universitarias Bajo la Monarquía Hispánica, Las: Salamanca, México Y Pavón Romero, Armando; Blasco Gil, Yolanda Bonilla Artigas Editores |
Título: Layout Techniques For Mosfets | ||
Autor: Pinillos Gimenez, Salvador | Precio: $875.00 | |
Editorial: Morgan & Claypool Publishers | Año: 2016 | |
Tema: Ingenieria, Novela Mexicana | Edición: 1ª | |
Sinopsis | ISBN: 9781627054881 | |
This book aims at describing in detail the different layout techniques for remarkably boosting the electrical performance and the ionizing radiation tolerance of planar Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs) without adding any costs to the current planar Complementary MOS (CMOS) integrated circuits (ICs) manufacturing processes. These innovative layout styles are based on pn junctions engineering between the drain/source and channel regions or simply MOSFET gate layout change. These interesting layout structures are capable of incorporating new effects in the MOSFET structures, such as the Longitudinal Corner Effect (LCE), the Parallel connection of MOSFETs with Different Channel Lengths Effect (PAMDLE), the Deactivation of the Parallel MOSFETs in the Bird's Beak Regions (DEPAMBBRE), and the Drain Leakage Current Reduction Effect (DLECRE), which are still seldom explored by the semiconductor and CMOS ICs industries. Several three-dimensional (3D) numerical simulations and experimental works are referenced in this book to show how these layout techniques can help the designers to reach the analog and digital CMOS ICs specifications with no additional cost. Furthermore, the electrical performance and ionizing radiation robustness of the analog and digital CMOS ICs can significantly be increased by using this gate layout approach |